The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Jan. 28, 2016
Applicant:

Altera Corporation, San Jose, CA (US);

Inventor:

John Curtis Van Dyken, Caledon East, CA;

Assignee:

Altera Corporation, San Jose, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/177 (2006.01); H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
H03K 19/17728 (2013.01); H03K 19/1737 (2013.01); H03K 19/1776 (2013.01); H03K 19/17744 (2013.01);
Abstract

Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may include lookup table (LUT) circuitry driven using vectored multiplexing circuits. The vectored multiplexing circuits may include a first multiplexer stage controlled by common configuration bits, a second multiplexer stage, and means for connecting either outputs of the first multiplexer stage or the output of the second multiplexer stage to corresponding logic circuits. The vectored multiplexing circuits may be used to generate multiple signal variants to vectored lookup table circuitry. The vectored lookup table circuitry may include a first stage of LUTs sharing some number of inputs and a second stage of LUTs at least some of which can be switched out of use. The second stage of LUTs may have inputs that are deactivated in a fractured mode.


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