The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Mar. 09, 2017
Applicant:

Shenzhen China Star Optoelectronics Technology Co., Ltd., Shenzhen, CN;

Inventors:

Shimin Ge, Shenzhen, CN;

Hejing Zhang, Shenzhen, CN;

Chihyuan Tseng, Shenzhen, CN;

Chihyu Su, Shenzhen, CN;

Wenhui Li, Shenzhen, CN;

Longqiang Shi, Shenzhen, CN;

Xiaowen Lv, Shenzhen, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/10 (2006.01); H01L 29/786 (2006.01); H01L 27/32 (2006.01); H01L 29/24 (2006.01); H01L 29/66 (2006.01); H01L 27/12 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/4763 (2006.01); H01L 21/027 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/0274 (2013.01); H01L 21/47635 (2013.01); H01L 27/1288 (2013.01); H01L 27/3248 (2013.01); H01L 29/24 (2013.01); H01L 29/4908 (2013.01); H01L 29/518 (2013.01); H01L 29/66969 (2013.01); H01L 29/78618 (2013.01); H01L 29/78648 (2013.01); H01L 29/78696 (2013.01); H01L 27/1225 (2013.01); H01L 2227/323 (2013.01);
Abstract

A dual gate oxide semiconductor TFT substrate is made by utilizing a halftone mask to implement one photo process, which accomplishes patterning of an oxide semiconductor layer and forms an oxide conductor layer with ion doping process. Patterning of a bottom gate isolation layer and a top gate isolation layer are performed at the same time with one photo process. A first top gate, a first source, a first drain, a second top gate, a second source, and a second drain are formed at the same time with one photo process. Patterning of a flat layer, a passivation layer, and a top gate isolation layer are performed at the same time with one photo process. As such, the number of photo processes applied to manufacture the TFT substrate is reduced to five and the manufacturing process is shortened to thereby raise the production efficiency and lower the production cost.


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