The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9768317 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 19, 2017

Filed:

Dec. 07, 2015
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken, JP;

Inventors:

Daigo Ito, Kanagawa, JP;

Takahisa Ishiyama, Kanagawa, JP;

Kazuya Hanaoka, Kanagawa, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/786 (2006.01); H01L 29/66 (2006.01); H01L 21/467 (2006.01); H01L 21/02 (2006.01); H01L 27/12 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7869 (2013.01); H01L 21/0228 (2013.01); H01L 21/02178 (2013.01); H01L 21/02266 (2013.01); H01L 21/467 (2013.01); H01L 27/1225 (2013.01); H01L 29/66969 (2013.01); H01L 29/78606 (2013.01); H01L 29/78696 (2013.01); H01L 21/02554 (2013.01); H01L 21/02565 (2013.01); H01L 21/02631 (2013.01);
Abstract

Provided is a semiconductor device which can suppress an increase in oxygen vacancies in an oxide semiconductor layer and a manufacturing method of the semiconductor device. The semiconductor device includes a first oxide semiconductor layer over the first insulating layer; a second oxide semiconductor layer over the first oxide semiconductor layer; a third oxide semiconductor layer over the second oxide semiconductor layer; a source electrode layer and a drain electrode layer each over the third oxide semiconductor layer; a fourth semiconductor layer over the source and drain electrode layers, and the third oxide semiconductor layer; a gate insulating layer over the fourth oxide semiconductor layer; a gate electrode layer over the gate electrode layer and overlapping with the source and drain electrode layers, and the fourth oxide semiconductor layer; and a second insulating layer over the first insulating layer, and the source, gate, and drain electrode layers.


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