The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9768308 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 19, 2017

Filed:

Mar. 18, 2015
Applicant:

Boe Technology Group Co., Ltd., Beijing, CN;

Inventors:

Xiaoyong Lu, Beijing, CN;

Zheng Liu, Beijing, CN;

Liang Sun, Beijing, CN;

Xiaolong Li, Beijing, CN;

Chunping Long, Beijing, CN;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/336 (2006.01); H01L 29/786 (2006.01); H01L 21/285 (2006.01); H01L 27/12 (2006.01); H01L 29/66 (2006.01); H01L 29/45 (2006.01);
U.S. Cl.
CPC ...
H01L 29/78618 (2013.01); H01L 21/28518 (2013.01); H01L 21/28568 (2013.01); H01L 27/1222 (2013.01); H01L 27/1274 (2013.01); H01L 29/458 (2013.01); H01L 29/665 (2013.01); H01L 29/66757 (2013.01); H01L 29/78675 (2013.01); H01L 29/78696 (2013.01);
Abstract

A low temperature poly-silicon thin film transistor and a fabrication method thereof, an array substrate and a display device are provided. The method comprises: S: sequentially forming an active layer (), a gate insulation layer (), a gate electrode () and an interlayer insulation layer () on a base substrate (); S: forming a first metal thin film layer (); S: performing a hydrogenation treatment on the active layer () and the gate insulation layer (); S: forming a second metal thin film layer (), the second metal thin film layer () being used for forming a source electrode and a drain electrode.


Find Patent Forward Citations

Lu, Xiaoyong. (2017). Low temperature poly-silicon thin film transistor and fabrication method thereof, array substrate and display device (U.S. Patent No. 9768308). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/9768308

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