The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
Nov. 25, 2015
Applicant:
Renesas Electronics Corporation, Koutou-ku, Tokyo, JP;
Inventor:
Shinya Hori, Hitachinaka, JP;
Assignee:
Renesas Electronics Corporation, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/146 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/14603 (2013.01); H01L 27/14621 (2013.01); H01L 27/14623 (2013.01); H01L 27/14627 (2013.01); H01L 27/14632 (2013.01); H01L 27/14643 (2013.01); H01L 27/14685 (2013.01); H01L 27/14687 (2013.01); H01L 27/14689 (2013.01);
Abstract
A groove-type through hole passing through a silicon layer and a first interlayer insulating film is formed in a region around a chip formation region including a photodiode. In the groove-type through hole, a wall-like wall-type conductive pass-through portion corresponding to the groove-type through hole is formed. An electrode pad is in contact with the wall-type conductive pass-through portion. The electrode pad is electrically connected to a first interconnection through the wall-type conductive pass-through portion.