The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Apr. 07, 2016
Applicant:

Toshiba Memory Corporation, Minato-ku, JP;

Inventors:

Hiroshi Shinohara, Yokosuka, JP;

Atsuhiro Sato, Tokyo, JP;

Keisuke Yonehama, Kamakura, JP;

Yasuyuki Baba, Zama, JP;

Toshifumi Minami, Yokohama, JP;

Hiroyuki Maeda, Kawasaki, JP;

Shinji Saito, Yokohama, JP;

Hideyuki Kamata, Kawasaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/1158 (2017.01); H01L 23/528 (2006.01); H01L 27/11582 (2017.01); H01L 21/02 (2006.01); H01L 27/11568 (2017.01); H01L 23/522 (2006.01); H01L 27/11565 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1158 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 23/528 (2013.01); H01L 23/5226 (2013.01); H01L 23/5286 (2013.01); H01L 27/11565 (2013.01); H01L 27/11568 (2013.01); H01L 27/11582 (2013.01); H01L 2924/0002 (2013.01);
Abstract

According to one embodiment, a semiconductor memory device includes: a semiconductor substrate; a first semiconductor pillar above the semiconductor substrate; a first insulating layer comprising a first section and a second section, the first section being in contact with the semiconductor substrate and a bottom of the first semiconductor pillar, and the second section covering a side of the first semiconductor pillar; conductive layers and second insulating layers stacked one by one above the semiconductor substrate and covering the second section of the first insulating layer; a first plug on the first semiconductor pillar; and an interconnect on the first plug.


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