The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 19, 2017
Filed:
May. 14, 2015
Applicant:
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Inventors:
Toru Hiyoshi, Osaka, JP;
Taku Horii, Osaka, JP;
Assignee:
Sumitomo Electric Industries, Ltd., Osaka-shi, JP;
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); H01L 23/00 (2006.01); H01L 21/02 (2006.01); H01L 21/3205 (2006.01); H01L 21/78 (2006.01); H01L 29/16 (2006.01); H01L 29/20 (2006.01); H01L 29/78 (2006.01); H01L 23/58 (2006.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01);
U.S. Cl.
CPC ...
H01L 23/562 (2013.01); H01L 21/0214 (2013.01); H01L 21/0217 (2013.01); H01L 21/02164 (2013.01); H01L 21/32051 (2013.01); H01L 21/78 (2013.01); H01L 23/585 (2013.01); H01L 29/1602 (2013.01); H01L 29/1608 (2013.01); H01L 29/2003 (2013.01); H01L 29/7811 (2013.01); H01L 21/561 (2013.01); H01L 23/3192 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/05558 (2013.01); H01L 2224/06181 (2013.01); H01L 2224/94 (2013.01);
Abstract
A method of manufacturing a semiconductor device includes preparing a semiconductor layer having an element region and an outer peripheral region, forming a step portion surrounding the outer periphery of the element region in the outer peripheral region, and forming a metal layer along the step portion. The metal layer extends to cover at least a portion of a sidewall of the step portion. The method of manufacturing the semiconductor device further includes dividing the semiconductor layer into element regions on an outside of the step portion when viewed from the element region.