The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Jan. 11, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Young-Jin Cho, Hwaseong-si, KR;

Jong-Min Jung, Incheon, KR;

Yun-Ji Hur, Hwaseong-si, KR;

Sung-Sik Park, Seoul, KR;

Keun-Bong Lee, Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/495 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01); G02F 1/1345 (2006.01); H01L 23/14 (2006.01);
U.S. Cl.
CPC ...
H01L 23/4985 (2013.01); G02F 1/13452 (2013.01); H01L 23/49838 (2013.01); H01L 24/00 (2013.01); H01L 23/145 (2013.01); H01L 23/49894 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/73204 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A chip-on-film (COF) package includes a base film, a semiconductor chip mounted on a chip mounting region of a top surface of the base film, a plurality of top inner output conductive patterns, a plurality of bottom inner output conductive patterns and a plurality of landing vias. The top inner output conductive patterns are formed on the top surface of the base film and respectively connected to chip inner output pads formed on a bottom surface of the semiconductor chip. The bottom inner output conductive patterns are formed on a bottom surface of the base film. The landing vias are formed to vertically penetrate the base film and to respectively connect the top inner output conductive patterns and the bottom inner output conductive patterns. The landing vias are arranged within the chip mounting region to form a two-dimensional shape.


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