The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 21/768 (2006.01); H01L 21/3213 (2006.01); H01L 23/50 (2006.01); H01L 21/8234 (2006.01); H01L 21/3105 (2006.01); H01L 21/033 (2006.01); H01L 21/02 (2006.01);

U.S. Cl.

CPC ...

H01L 21/823437 (2013.01); H01L 21/0217 (2013.01); H01L 21/0332 (2013.01); H01L 21/0337 (2013.01); H01L 21/31051 (2013.01); H01L 21/32139 (2013.01);

Abstract

Provided is a method for manufacturing a semiconductor device, which can secure a sufficient margin in a process of forming a self-aligned contact. The method includes forming a plurality of gate structures arranged in parallel on a substrate and being spaced apart from each other, each of the plurality of gate structures including a conductive layer and a capping layer formed on the conductive layer, forming a first insulation layer between each of the plurality of gate structures, recessing top portions of the plurality of gate structures, forming a block layer along a top surface of the first insulation layer and the recessed top portions of the plurality of gate structures, forming a hardmask layer on the block layer, forming a hardmask pattern on each of the plurality of gate structures by planarizing a top portion of the block layer and a top portion of the hardmask layer, and forming a second insulation layer along a top surface of the block layer and top surfaces of the hardmask patterns.

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