Mitigation scheme for sram functionality

Abstract

An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.