The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

May. 29, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, Gyeonggi-Do, KR;

Inventors:

Kwan-Young Oh, Hwaseong-si, KR;

Sil-Yi Bang, Yongin-si, KR;

Sang-Su Han, Seoul, KR;

Jin-Hyun Ko, Yongin-si, KR;

Jin-Kyu Park, Yongin-si, KR;

Jae-Ho Choi, Seoul, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G09G 3/36 (2006.01); G09G 5/12 (2006.01); G09G 3/20 (2006.01);
U.S. Cl.
CPC ...
G09G 5/12 (2013.01); G09G 3/20 (2013.01); G09G 3/3666 (2013.01); G09G 3/3607 (2013.01); G09G 2310/08 (2013.01);
Abstract

A display apparatus includes: a display panel including a first display area and a second display area; a first timing controller to control an operation of the first display area, generate a first reference clock signal, generate a first internal reference clock signal based on the first reference clock signal, and generate a first synchronization clock signal based on the first internal reference clock signal; and a second timing controller to control an operation of the second display area, receive the first reference clock signal, generate a second internal reference clock signal based on the first reference clock signal, and generate a second synchronization clock signal based on the second internal reference clock signal, wherein the first and second timing controllers are to be synchronized with each other based on the first reference clock signal, and exchange first data based on the first and second synchronization clock signals.


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