The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 19, 2017

Filed:

Sep. 25, 2015
Applicant:

Cypress Semiconductor Corporation, San Jose, CA (US);

Inventor:

Warren S Snyder, Snohomish, WA (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 13/40 (2006.01); G06F 1/08 (2006.01); G06F 1/32 (2006.01); G06F 15/78 (2006.01); G06G 7/06 (2006.01); H03B 5/36 (2006.01); H03H 19/00 (2006.01); H03K 3/012 (2006.01); H03K 3/014 (2006.01); H03K 3/0231 (2006.01); G06F 9/445 (2006.01); G06F 13/10 (2006.01);
U.S. Cl.
CPC ...
G06F 1/08 (2013.01); G06F 1/32 (2013.01); G06F 9/44505 (2013.01); G06F 13/102 (2013.01); G06F 13/40 (2013.01); G06F 15/7867 (2013.01); G06G 7/06 (2013.01); H03B 5/364 (2013.01); H03H 19/004 (2013.01); H03K 3/012 (2013.01); H03K 3/014 (2013.01); H03K 3/02315 (2013.01);
Abstract

A programmable device includes reconfigurable analog circuitry, reconfigurable digital circuitry, a plurality of input/output (I/O) blocks, and a global mapping system. The global mapping system is configured to selectively couple the plurality of I/O blocks with analog functional units of the reconfigurable analog circuitry and with digital functional units of the reconfigurable digital circuitry.


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