The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Mar. 10, 2015
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Sisir Chowdhury, Fremont, CA (US);

David Iles, San Jose, CA (US);

Keshav G. Kamble, Fremont, CA (US);

Vijoy A. Pandey, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H04L 12/891 (2013.01); H04L 12/803 (2013.01); H04L 12/709 (2013.01); H04L 29/06 (2006.01); H04L 29/08 (2006.01); H04L 12/911 (2013.01);
U.S. Cl.
CPC ...
H04L 47/125 (2013.01); H04L 45/245 (2013.01); H04L 47/41 (2013.01); H04L 67/1044 (2013.01); H04L 69/24 (2013.01); H04L 47/827 (2013.01); Y02B 60/33 (2013.01);
Abstract

In one embodiment, a switch includes a processor and logic integrated with and/or executable by the processor to receive details about which link aggregation (LAG) information about a first peer switch will be exchanged with the switch, send to the first peer switch, prior to receiving the LAG information about the first peer switch, details about which LAG information about the switch will be exchanged with the first peer switch, receive the LAG information about the first peer switch, store the LAG information about the first peer switch, and use the LAG information about the first peer switch and the LAG information about the switch to determine load balancing across one or more connections between the switch and the first peer switch.


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