The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jul. 29, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Alvin Leng Sun Loke, San Diego, CA (US);

Bo Yu, San Diego, CA (US);

Stephen Clifford Thilenius, San Diego, CA (US);

Reza Jalilizeinali, Carlsbad, CA (US);

Patrick Isakanian, El Dorado Hills, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03B 1/00 (2006.01); H03K 3/00 (2006.01); H03K 17/082 (2006.01); H03K 19/003 (2006.01); H03K 19/0185 (2006.01);
U.S. Cl.
CPC ...
H03K 17/0822 (2013.01); H03K 19/00315 (2013.01); H03K 19/018521 (2013.01);
Abstract

An electronic circuit and methods of operating the electronic circuit are provided. The electronic circuit includes a pull-up transistor for pulling up an input/output (I/O) node of the output circuit to a first voltage and a first isolation transistor for coupling the pull-up transistor to the I/O node. The electronic circuit also includes a pull-down transistor for pulling down the I/O node to a second voltage and a second isolation transistor for coupling the pull-down transistor to the I/O node. In the electronic circuit, the pull-up and the pull-down transistors are transistors supporting a first drain-to-source voltage and a first gate-to-source voltage, while the first and the second isolation transistors are transistors supporting the first drain-to-source voltage and a second gate-to-source voltage greater than the first gate-to-source voltage.


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