The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Sep. 15, 2015
Applicant:

Qualcomm Incorporated, San Diego, CA (US);

Inventors:

Neha Agrawal, Bangalore KRN, IN;

Sajin Mohamad, Bangalore KRN, IN;

Chulkyu Lee, San Diego, CA (US);

Assignee:

QUALCOMM Incorporated, San Diego, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 21/00 (2006.01); H03K 7/06 (2006.01); H03K 19/21 (2006.01); H03K 3/037 (2006.01); H03K 21/10 (2006.01); H03K 23/64 (2006.01); H03K 23/00 (2006.01); H03K 21/02 (2006.01); G06F 1/08 (2006.01);
U.S. Cl.
CPC ...
H03K 7/06 (2013.01); H03K 3/037 (2013.01); H03K 19/21 (2013.01); H03K 21/10 (2013.01); H03K 23/64 (2013.01); G06F 1/08 (2013.01); H03K 21/00 (2013.01); H03K 21/026 (2013.01); H03K 23/00 (2013.01);
Abstract

Systems and methods for dividing input clock signals by programmable divide ratios can produce output clock signals with the delay from the input clock signal to the output clock signal independent of the value of the divide ratio and with the duty cycle of the output clock signal being 50% independent of the value of the divide ratio. An example programmable clock divider includes a modulo N counter that produces a count signal that counts modulo the divide ratio and a half-rate clock signal generator that produces a common half-rate clock signal, an even half-rate clock signal, and an odd half-rate clock signal that toggle at one-half the rate of the output clock signal. The common half-rate clock signal, the even half-rate clock signal, and the odd half-rate clock signal are combined to produce the output clock signal.


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