The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 12, 2017
Filed:
Jun. 17, 2014
Maschinenfabrik Reinhausen Gmbh, Regensburg, DE;
MASCHINENFABRIK REINHAUSEN GMBH, Regensburg, DE;
Abstract
The invention generally relates to methods and circuits for controlling switching of parallel coupled power semiconductor switching devices (), for example for use in a power converter. In an example, there is provided a circuit for controlling switching of parallel coupled power semiconductor switching devices (), the circuit comprising: a plurality of drive modules (), each said module for controlling a said power semiconductor switching device (); control circuitry to transmit switch command signals to the modules, each said switch command signal to trigger a said drive module to control a said power semiconductor switching device to switch state; and voltage isolation between the drive modules and the control circuitry, wherein each said drive module for controlling a said device comprises: timing circuitry () to compare a switching delay of the device and a reference delay, wherein said switching delay is a time interval between detecting a said switching command signal at the drive module and switching of the device in accordance with the detected switching command signal; and delay circuitry () to provide a controllable delay to delay a said triggering by a said switching command signal received at the module subsequent to the detected switching command signal, the delay circuitry configured to control the controllable delay according to a result of said comparison of said switching delay of the device, to thereby reduce a time difference between the reference delay and a said switching delay of the device switching in accordance with the subsequent switching command signal.