The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Oct. 31, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

Brent A. Anderson, Essex Junction, VT (US);

Albert M. Chu, Nashua, NH (US);

Terence B. Hook, Essex Junction, VT (US);

Seong-Dong Kim, Hopewell Junction, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01); H01L 29/78 (2006.01); H01L 29/08 (2006.01); H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 23/528 (2006.01); H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7827 (2013.01); G06F 17/5072 (2013.01); G06F 17/5077 (2013.01); H01L 23/5286 (2013.01); H01L 27/0207 (2013.01); H01L 27/088 (2013.01); H01L 29/0649 (2013.01); H01L 29/0847 (2013.01);
Abstract

A method for device layout with vertical transistors includes identifying active area regions in a layout of a semiconductor device with vertical transistors. Sets of adjacent active area regions having a same electrical potential are determined. The sets of adjacent active area regions to be merged are prioritized based upon one or more performance criterion. The sets of adjacent active area regions are merged to form larger active area regions according to a priority.


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