The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9761620 B1

PDF
Full Text
Expired
Date of Patent:
Sep. 12, 2017

Filed:

Sep. 19, 2016
Applicant:

Peter C. Salmon, Mountain View, CA (US);

Inventor:

Peter C. Salmon, Mountain View, CA (US);

Assignee:

Peter C. Salmon, LLC, Mountain View, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/46 (2006.01); H01L 21/4763 (2006.01); H01L 27/146 (2006.01); C23C 16/54 (2006.01); C23C 16/455 (2006.01); H01L 27/11578 (2017.01); G02F 1/1335 (2006.01); G03G 15/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1462 (2013.01); C23C 16/45544 (2013.01); C23C 16/545 (2013.01); H01L 21/4763 (2013.01); H01L 27/11578 (2013.01); H01L 27/1464 (2013.01); H01L 27/14614 (2013.01); H01L 27/14632 (2013.01); H01L 27/14636 (2013.01); H01L 27/14643 (2013.01); G02F 1/133516 (2013.01); G03G 15/08 (2013.01);
Abstract

A charge array wafer includes a plurality of electrical charge storage cells disposed in an array configuration. A programmable amount of charge in each of the electrical charge storage cells causes a predetermined electric field to extend from a charge storage layer, through a passivation layer and into the space above the passivation layer, and the predetermined electric field is operable to attract deposition material to the top surface of the passivation layer. The deposition material may be a gas, a liquid or a powder, having a minimum feature size ranging from tens of nanometers to around five microns. The array of electrical charge storage cells includes an uninterrupted two-dimensional array extending over greater than 100×100 electrical charge storage cells without a select gate and without a bit-line contact positioned between any of the electrical charge storage cells.


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