The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Feb. 23, 2012
Applicants:

Takukazu Otsuka, Kyoto, JP;

Bryon Western, West Park, AZ (US);

Brandon Passmore, Fayetteville, AR (US);

Zach Cole, Summers, AR (US);

Inventors:

Takukazu Otsuka, Kyoto, JP;

Bryon Western, West Park, AZ (US);

Brandon Passmore, Fayetteville, AR (US);

Zach Cole, Summers, AR (US);

Assignees:

ROHM CO., LTD., Kyoto, JP;

CREE FAYETTEVILLE, INC., Fayetteville, AR (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/34 (2006.01); H01L 23/373 (2006.01); H01L 23/00 (2006.01); H01L 25/07 (2006.01); H01L 25/00 (2006.01);
U.S. Cl.
CPC ...
H01L 23/3735 (2013.01); H01L 24/13 (2013.01); H01L 24/16 (2013.01); H01L 24/29 (2013.01); H01L 24/33 (2013.01); H01L 24/81 (2013.01); H01L 24/83 (2013.01); H01L 25/072 (2013.01); H01L 24/32 (2013.01); H01L 25/50 (2013.01); H01L 2224/16245 (2013.01); H01L 2224/32225 (2013.01); H01L 2224/32245 (2013.01); H01L 2224/73253 (2013.01); H01L 2224/8182 (2013.01); H01L 2224/8383 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/1305 (2013.01); H01L 2924/13055 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1461 (2013.01); H01L 2924/351 (2013.01);
Abstract

Provided is a double-sided cooling structure for a semiconductor device using a low processing temperature and reduced processing time utilizing solid phase diffusion bonding. The fabrication method for this system is provided. The semiconductor devicecomprising: a mounting substrate; a semiconductor chipdisposed on the mounting substrateand a semiconductor substrate, a source pad electrode SP and a gate pad electrode GP disposed on a surface of the semiconductor substrate, and a drain pad electrodedisposed on a back side surface of the semiconductor substrateto be contacted with the mounting substrate; and a source connector SC disposed on the source pad electrode SP. The mounting substrateand the drain pad electrodeare bonded by using solid phase diffusion bonding.


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