The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Oct. 20, 2015
Applicant:

Globalfoundries Inc., Grand Cayman, KY;

Inventors:

Aravindan J. Busi, Bangalore, IN;

Deepak I. Hanagandi, Bagalkot, IN;

Krishnendu Mondal, Bangalore, IN;

Michael R. Ouellette, Westford, VT (US);

Assignee:

GLOBALFOUNDRIES INC., Grand Cayman, KY;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 29/38 (2006.01); G11C 29/18 (2006.01); G11C 29/44 (2006.01); G11C 29/04 (2006.01);
U.S. Cl.
CPC ...
G11C 29/38 (2013.01); G11C 29/18 (2013.01); G11C 29/44 (2013.01); G11C 2029/0401 (2013.01);
Abstract

An integrated circuit chip with a built-in self-test (BIST) circuit having a BIST engine, which is electrically connected to multiple memories, which tests those multiple memories in parallel, and which incorporates an address generator. Prior to testing, the address generator generates a pair of tables. The tables include a first table, which indicates the highest decode numbers per specific bank numbers in all of the multiple memories, and a second table, which indicates the highest bank numbers per specific decode numbers in all of the multiple memories. During testing, the address generator sequentially and dynamically generates the specific test addresses to be swept and does so such that all of the specific test addresses are within a composite address space that is defined by one of the tables and by the highest maximum word line number in any of the memories. Also disclosed is an associated BIST method.


Find Patent Forward Citations

Loading…