The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jun. 14, 2013
Applicant:

Microsoft Corporation, Redmond, WA (US);

Inventors:

Kenneth Hiroshi Eguro, Seattle, WA (US);

Ray A. Bittner, Jr., Bothell, WA (US);

George E. Smith, Bellevue, WA (US);

Shawn Michael Swilley, Kent, WA (US);

Rehan Ahmed, Kelowna, CA;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06K 9/00 (2006.01); H04N 5/33 (2006.01); G06K 9/62 (2006.01); G06F 11/30 (2006.01); G06F 3/06 (2006.01); G06F 9/30 (2006.01); G06F 12/02 (2006.01); G06F 12/00 (2006.01); H04N 13/02 (2006.01); H04N 13/00 (2006.01); G02B 27/42 (2006.01); B29C 67/00 (2017.01); G02B 5/18 (2006.01); G02B 27/44 (2006.01); H04N 5/225 (2006.01); H04N 9/04 (2006.01); H04N 17/00 (2006.01); G01B 11/25 (2006.01); G01B 11/22 (2006.01); G06T 1/60 (2006.01); G06T 7/00 (2017.01); G06T 7/586 (2017.01); A63F 13/213 (2014.01);
U.S. Cl.
CPC ...
G06K 9/00536 (2013.01); B29C 67/0051 (2013.01); G01B 11/22 (2013.01); G01B 11/25 (2013.01); G01B 11/2513 (2013.01); G01B 11/2527 (2013.01); G01B 11/2545 (2013.01); G02B 5/1895 (2013.01); G02B 27/4205 (2013.01); G02B 27/44 (2013.01); G06F 3/0653 (2013.01); G06F 3/0659 (2013.01); G06F 3/0683 (2013.01); G06F 9/3004 (2013.01); G06F 9/30043 (2013.01); G06F 9/30127 (2013.01); G06F 11/3024 (2013.01); G06F 12/00 (2013.01); G06F 12/02 (2013.01); G06F 12/0207 (2013.01); G06F 12/0292 (2013.01); G06K 9/0063 (2013.01); G06K 9/00201 (2013.01); G06K 9/62 (2013.01); G06T 1/60 (2013.01); G06T 7/00 (2013.01); G06T 7/586 (2017.01); H04N 5/2256 (2013.01); H04N 5/33 (2013.01); H04N 5/332 (2013.01); H04N 9/045 (2013.01); H04N 13/0022 (2013.01); H04N 13/02 (2013.01); H04N 13/025 (2013.01); H04N 13/0239 (2013.01); H04N 13/0253 (2013.01); H04N 13/0271 (2013.01); H04N 17/002 (2013.01); A63F 13/213 (2014.09); G06T 2207/30244 (2013.01); H04N 2013/0081 (2013.01);
Abstract

The subject disclosure is directed towards loading parallel memories (e.g., in one or more FPGAs) with multidimensional data in an interleaved manner such that a multidimensional patch/window may be filled with corresponding data in a single parallel read of the memories. Depending on the position of the patch, the data may be rotated horizontally and/or vertically, for example, so that the data in each patch is consistently arranged in the patch regardless of from which memory each piece of data was read. Also described is leveraging dual ported memory for multiple line reads and/or loading one part of a buffer while reading from another.


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