The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Aug. 14, 2014
Applicants:

The Regents of the University of Michigan, Ann Arbor, MI (US);

Isocline Engineering, Llc, Ann Arbor, MI (US);

Inventors:

Laura Fick, Ann Arbor, MI (US);

David T. Blaauw, Ann Arbor, MI (US);

Dennis Sylvester, Ann Arbor, MI (US);

Michael B. Henry, Ann Arbor, MI (US);

David Alan Fick, Ann Arbor, MI (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06N 3/06 (2006.01); G06F 17/11 (2006.01); G11C 16/10 (2006.01); G06N 3/063 (2006.01); G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
G06F 17/11 (2013.01); G06N 3/063 (2013.01); G11C 7/1006 (2013.01); G11C 16/10 (2013.01);
Abstract

A weighted sum is a key computation for many neural networks and other machine learning algorithms. Integrated circuit designs that perform a weighted sum are presented. Weights are stored as threshold voltages in an array of flash transistors. By putting the circuits into a well-defined voltage state, the transistors that hold one set of weights will pass current equal to the desired sum. The current flowing through a given transistor is unaffected by operation of remaining transistors in the circuit.


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