The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 12, 2017

Filed:

Jul. 15, 2016
Applicant:

International Business Machines Corporation, Armonk, NY (US);

Inventors:

David M. Daly, Croton on Hudson, NY (US);

Vijayalakshmi Srinivasan, New York, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01); G06F 12/0815 (2016.01); G06F 12/0817 (2016.01); G06F 12/084 (2016.01); G06F 3/06 (2006.01); G06F 12/0831 (2016.01);
U.S. Cl.
CPC ...
G06F 12/0815 (2013.01); G06F 3/06 (2013.01); G06F 12/084 (2013.01); G06F 12/0817 (2013.01); G06F 12/0831 (2013.01); G06F 2212/1008 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1021 (2013.01); G06F 2212/1048 (2013.01); G06F 2212/151 (2013.01); G06F 2212/251 (2013.01); G06F 2212/283 (2013.01); G06F 2212/608 (2013.01); G06F 2212/621 (2013.01);
Abstract

A mechanism is provided for memory coherence in a multiple processor system. Responsive to a memory operation from a processing core of the multiple processor system resulting in a cache miss, the mechanism checks a private region table associated with the processing core. The memory operation attempts to access a memory region. Responsive to determining the memory region corresponds to an entry in the private region table, the mechanism performs a remote memory controller snoop of a remote memory controller without snooping the multiple processor system.


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