The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Dec. 04, 2014
Applicant:

Texas Instruments Incorporated, Dallas, TX (US);

Inventors:

Sriram Murali, Karnataka, IN;

Sarma Gunturi, Karnataka, IN;

Jaiganesh Balakrishnan, Bangalore, IN;

Murugesh Subramaniam, Karnataka, IN;

Harikrishna Parthasarathy, Karnataka, IN;

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H04W 52/02 (2009.01); H04W 76/04 (2009.01); H04L 5/16 (2006.01); H04L 25/49 (2006.01); H04L 27/14 (2006.01); H04B 1/44 (2006.01);
U.S. Cl.
CPC ...
H04W 52/028 (2013.01); H04B 1/44 (2013.01); H04L 5/16 (2013.01); H04W 76/048 (2013.01); H04L 25/4902 (2013.01); H04L 27/14 (2013.01); Y02B 60/50 (2013.01);
Abstract

Circuits and methods for reducing power consumption in a half-duplex transceiver are disclosed. In an embodiment, a power management circuit of half-duplex transceiver includes direct current to direct current (DC-DC) converter and snooze mode controller. The DC-DC converter includes switching circuit and driver circuit to drive the switching circuit. The DC-DC converter provides power supply to at least one element of a transmitter sub-system of the half-duplex transceiver, and operates in snooze control modes. The snooze mode controller is coupled to the DC-DC converter and configured to generate a control signal based on at least one transceiver operating input, where the control signal causes the DC-DC converter to operate in one of the snooze control modes, the snooze control modes corresponding to snooze duty cycles and where in each snooze control mode, the switching circuit and the driver circuit remain in an OFF-state based on a respective snooze duty cycle.


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