The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Dec. 05, 2016
Applicant:

Semiconductor Manufacturing International (Shanghai) Corporation, Shanghai, CN;

Inventors:

Haiyang Zhang, Shanghai, CN;

Chenglong Zhang, Shanghai, CN;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 29/51 (2006.01); H01L 29/49 (2006.01); H01L 21/308 (2006.01); H01L 21/265 (2006.01); H01L 21/31 (2006.01); H01L 21/3105 (2006.01); H01L 21/3213 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7856 (2013.01); H01L 21/265 (2013.01); H01L 21/3086 (2013.01); H01L 21/31 (2013.01); H01L 21/31056 (2013.01); H01L 21/32135 (2013.01); H01L 29/495 (2013.01); H01L 29/4983 (2013.01); H01L 29/512 (2013.01); H01L 29/517 (2013.01); H01L 29/6653 (2013.01); H01L 29/66545 (2013.01); H01L 29/66628 (2013.01); H01L 29/66795 (2013.01);
Abstract

A method for fabricating a FinFET structure comprises providing a semiconductor substrate; forming a hard mask layer on the semiconductor substrate; forming a dummy gate structure having a dummy gate, a first sidewall spacer and a second sidewall spacer; removing the dummy gate to form a first trench; forming first sub-fins in the semiconductor substrate under the hard mask layer in the first trench; forming a first metal gate structure in the first trench; removing the first sidewall spacer to form a second trench; forming second sub-fins in the semiconductor substrate under the hard mask layer in the second trench; forming a second metal gate structure in the second trench; removing the second sidewall spacer to form a third trench; forming third sub-fins in the semiconductor substrate under the hard mask layer in the third trench; and forming a third metal gate structure in the third trench.


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