The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Apr. 28, 2016
Applicant:
Renesas Electronics Corporation, Tokyo, JP;
Inventor:
Hiroki Fujii, Tokyo, JP;
Assignee:
RENESAS ELECTRONICS CORPORATION, Tokyo, JP;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H01L 29/10 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7825 (2013.01); H01L 29/0653 (2013.01); H01L 29/0696 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/42376 (2013.01); H01L 29/66659 (2013.01); H01L 29/66704 (2013.01); H01L 29/7816 (2013.01); H01L 29/7835 (2013.01);
Abstract
There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.