The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Jan. 27, 2016
Applicant:
Magnachip Semiconductor, Ltd., Cheongju-si, KR;
Inventors:
Assignee:
Magnachip Semiconductor, Ltd., Cheongju-si, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/78 (2006.01); H01L 29/66 (2006.01); H01L 27/092 (2006.01); H01L 29/423 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7816 (2013.01); H01L 27/092 (2013.01); H01L 29/0653 (2013.01); H01L 29/1083 (2013.01); H01L 29/1095 (2013.01); H01L 29/42368 (2013.01); H01L 29/66659 (2013.01); H01L 29/66681 (2013.01); H01L 29/7817 (2013.01); H01L 29/7835 (2013.01); H01L 29/0847 (2013.01);
Abstract
A semiconductor device and a fabrication method thereof are provided. The semiconductor device includes a P type well region and an N type well region formed in a substrate, a gate insulating layer having a non-uniform thickness and formed on the P type well region and the N type well region, a gate electrode formed on the gate insulating layer, a P type well pick-up region formed in the P type well region, and a field relief oxide layer formed in the N type well region between the gate electrode and the drain region.