The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Feb. 19, 2016
Applicant:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Inventors:

Teruyuki Ohashi, Kawasaki, JP;

Yuichiro Mitani, Miura, JP;

Tatsuo Shimizu, Shinagawa, JP;

Ryosuke Iijima, Setagaya, JP;

Assignee:

Kabushiki Kaisha Toshiba, Minato-ku, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/78 (2006.01); H01L 29/16 (2006.01); H01L 29/04 (2006.01); H01L 29/10 (2006.01); H01L 21/04 (2006.01); H01L 29/66 (2006.01); H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7802 (2013.01); H01L 21/049 (2013.01); H01L 21/3003 (2013.01); H01L 29/045 (2013.01); H01L 29/1095 (2013.01); H01L 29/1608 (2013.01); H01L 29/66068 (2013.01);
Abstract

A semiconductor device of an embodiment includes a SiC layer having a surface, the surface inclined at an angle of 0° to 10° with respect to a {000-1} face or the surface having a normal line direction inclined at an angle of 80° to 90° with respect to a <000-1> direction, a gate electrode, a gate insulating layer provided between the surface and the gate electrode, and a region provided between the surface and the gate insulating layer, a maximum concentration of deuterium (D) in the region being 1×10cmor more and a maximum concentration of hydrogen (H) in the region being 1×10cmor less.


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