The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Dec. 01, 2015
Applicant:

Samsung Display Co., Ltd., Yongin-si, Gyeonggi-do, KR;

Inventors:

Myung Kwan Ryu, Yongin-si, KR;

Ki Hwan Kim, Hwaseong-si, KR;

Kap Soo Yoon, Cheonan-si, KR;

Hyeon Jun Lee, Hwaseong-si, KR;

Jeong Uk Heo, Asan-si, KR;

Assignee:

Samsung Display Co., Ltd., Samsung-ro, Giheung-Gu, Yongin-si, Gyeonggi-Do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/66 (2006.01); H01L 29/417 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 21/306 (2006.01); H01L 21/324 (2006.01);
U.S. Cl.
CPC ...
H01L 29/66742 (2013.01); H01L 21/324 (2013.01); H01L 29/42384 (2013.01); H01L 29/7869 (2013.01); H01L 29/78621 (2013.01); H01L 29/78681 (2013.01); H01L 29/78684 (2013.01);
Abstract

There are provided a method of manufacturing a thin film transistor and a display including a thin film transistor. The method of manufacturing a thin film transistor includes forming a barrier layer cm a substrate, forming a semiconductor layer on the barrier layer, forming a gate insulating layer on the semiconductor layer, forming a gate electrode on the gate insulating layer, forming an offset region on an external surface of the gate electrode through a plasma heat treatment process or an annealing process, etching, an offset region of the gate electrode, etching a gate insulating layer except for a portion of the gate insulating layer, positioned below the gate electrode, forming an interlayer insulating layer on the gate electrode, and etching, the interlayer insulating layer to form a source electrode and a drain electrode.


Find Patent Forward Citations

Loading…