The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Mar. 30, 2016
Applicant:

Sony Corporation, Tokyo, JP;

Inventor:

Masaki Okamoto, Kumamoto, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 27/146 (2006.01); H01L 21/768 (2006.01); H04N 5/378 (2011.01);
U.S. Cl.
CPC ...
H01L 27/14636 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 27/1464 (2013.01); H01L 27/14632 (2013.01); H01L 27/14634 (2013.01); H01L 27/14643 (2013.01); H04N 5/378 (2013.01); H01L 2224/24145 (2013.01); H01L 2224/32145 (2013.01); H01L 2224/9205 (2013.01); H01L 2224/92244 (2013.01); H01L 2224/94 (2013.01); H01L 2225/06544 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/1431 (2013.01);
Abstract

A method of manufacturing a semiconductor device includes bonding a first semiconductor wafer including a first substrate and a first insulating layer formed to contact one surface of the first substrate, and a second semiconductor wafer including a second substrate and a second insulating layer, forming a third insulating layer, performing etching so that the second insulating layer remains on a second wiring layer, forming a first connection hole, forming an insulating film on the first connection hole, performing etching of the second insulating layer and the insulating film, forming a second connection hole, and forming a first via formed in inner portions of the connection holes and connected to the second wiring layer, wherein a diameter of the first connection hole formed on the other surface of the first substrate is greater than a diameter of the first connection hole formed on the third insulating layer.


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