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The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9754962 B1

PDFFull Text
Date of Patent:
Sep. 05, 2017

Filed:

May. 11, 2016

Three-dimensional (3d) semiconductor device

Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Chan Sun Hyun, Gyeonggi-do, KR;

Myung Kyu Ahn, Gyeonggi-do, KR;

Woo June Kwon, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:

IP & T Group LLP

Primary Examiner:

Thanhha Pham

Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 27/06 (2006.01); H01L 27/11582 (2017.01); H01L 21/822 (2006.01); H01L 27/24 (2006.01); H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 27/11551 (2017.01); H01L 27/11556 (2017.01); H01L 27/11558 (2017.01); H01L 27/11524 (2017.01); H01L 27/11548 (2017.01); H01L 27/1157 (2017.01); H01L 27/11575 (2017.01);
U.S. Cl.
CPC ...
H01L 27/11582 (2013.01); H01L 21/76838 (2013.01); H01L 21/76841 (2013.01); H01L 21/76843 (2013.01); H01L 21/76865 (2013.01); H01L 21/76871 (2013.01); H01L 21/76876 (2013.01); H01L 21/76877 (2013.01); H01L 21/76879 (2013.01); H01L 21/76895 (2013.01); H01L 21/8221 (2013.01); H01L 23/528 (2013.01); H01L 23/53257 (2013.01); H01L 23/53266 (2013.01); H01L 27/0688 (2013.01); H01L 27/1157 (2013.01); H01L 27/11524 (2013.01); H01L 27/11548 (2013.01); H01L 27/11551 (2013.01); H01L 27/11556 (2013.01); H01L 27/11558 (2013.01); H01L 27/11575 (2013.01); H01L 27/2481 (2013.01); G11C 2213/71 (2013.01); H01L 2924/0002 (2013.01);
Abstract

A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

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