The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Sep. 24, 2015
Applicant:
SK Hynix Inc., Gyeonggi-do, KR;
Inventors:
Assignee:
SK Hynix Inc., Gyeonggi-do, KR;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/115 (2017.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01); H01L 29/10 (2006.01); H01L 27/11529 (2017.01); H01L 27/11573 (2017.01); H01L 27/11526 (2017.01); H01L 29/78 (2006.01); H01L 27/11556 (2017.01); H01L 27/11582 (2017.01); H01L 27/1157 (2017.01); H01L 21/265 (2006.01);
U.S. Cl.
CPC ...
H01L 27/11529 (2013.01); H01L 27/11526 (2013.01); H01L 27/11573 (2013.01); H01L 29/0623 (2013.01); H01L 29/0653 (2013.01); H01L 29/6659 (2013.01); H01L 29/7833 (2013.01); H01L 21/26586 (2013.01); H01L 27/1157 (2013.01); H01L 27/11556 (2013.01); H01L 27/11582 (2013.01); H01L 29/1083 (2013.01);
Abstract
A semiconductor device includes a substrate having a memory array region and a peripheral region, isolation layers formed in the peripheral region to define an active region, offset insulating layers separated from each other and formed in the active region, and a gate electrode having edges overlapping with the offset insulating layers and arranged in the active region between the offset insulating layers.