The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Mar. 03, 2017
Applicant:

Cambridge Electronics, Inc., Cambridge, MA (US);

Inventors:

Bin Lu, Watertown, MA (US);

Ling Xia, Belmont, MA (US);

Assignee:

Cambridge Electronics, Inc., Cambridge, MA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 21/336 (2006.01); H03K 17/687 (2006.01); H01L 29/16 (2006.01); H01L 29/78 (2006.01); H01L 29/20 (2006.01); H01L 29/778 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0883 (2013.01); H01L 29/16 (2013.01); H01L 29/2003 (2013.01); H01L 29/7787 (2013.01); H01L 29/7819 (2013.01); H03K 17/687 (2013.01);
Abstract

A hybrid transistor circuit is disclosed for use in III-Nitride (III-N) semiconductor devices, comprising a Silicon (Si)-based Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET), a Group III-Nitride (III-N)-based Field-Effect Transistor (FET), and a driver unit. A source terminal of the III-N-based FET is connected to a drain terminal of the Si-based MOSFET. The driver unit has at least one input terminal, and two output terminals connected to the gate terminals of the transistors respectively. The hybrid transistor circuit is turned on through the driver unit by switching on the Silicon-based MOSFET first before switching on the III-N-based FET, and is turned off through the driver unit by switching off the III-N-based FET before switching off the Silicon-based MOSFET. Also disclosed are integrated circuit packages and semiconductor structures for forming such hybrid transistor circuits. The resulting hybrid circuit provides power-efficient and robust use of III-Nitride semiconductor devices.


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