The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Oct. 08, 2014
Applicants:

Yoon-hae Kim, Suwon-si, KR;

Jong-shik Yoon, Yongin-si, KR;

Hwa-sung Rhee, Seongnam-si, KR;

Byung-sung Kim, Suwon-si, KR;

Inventors:

Yoon-Hae Kim, Suwon-si, KR;

Jong-Shik Yoon, Yongin-si, KR;

Hwa-Sung Rhee, Seongnam-si, KR;

Byung-Sung Kim, Suwon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01); H01L 21/283 (2006.01); H01L 21/033 (2006.01); H01L 21/311 (2006.01); H01L 21/768 (2006.01);
U.S. Cl.
CPC ...
H01L 21/283 (2013.01); H01L 21/0337 (2013.01); H01L 21/31144 (2013.01); H01L 21/76816 (2013.01); H01L 21/76897 (2013.01);
Abstract

Provided are method of fabricating semiconductor device and computing system for implementing the method. The method of fabricating a semiconductor device includes forming a target layer, forming a first mask on the target layer to expose a first region, subsequently forming a second mask on the target layer to expose a second region separated from the first region in a first direction, subsequently forming a third mask in the exposed first region to divide the first region into a first sub region and a second sub region separated from each other in a second direction intersecting the first direction, and etching the target layer using the first through third masks such that the first and second sub regions and the second region are defined in the target layer.


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