Flash memory arrangement with a common read-write circuit shared by partial matrices of a memory column

Abstract

A flash memory arrangement includes first memory cells for non-volatile memory of information and a read-write circuit. The read-write circuit includes a write latch, read amplifier, bit circuit pre-charge circuit, and databus interface, with the first memory cell being connected to a first bit circuit, word circuit, VSE circuit, and a select circuit, and the read-write circuit being connected to a column decoder, databus, and a read control signal circuit. A first memory column is arranged such that in a first partial matrix the first memory cell is arranged, in which a first select transistor, a memory transistor, and a second select transistor are arranged between the first bit circuit and a discharge hub. The second select transistor can be controlled by a global, non address-decoded read-write select circuit. At every bit circuit, a reference memory cell is arranged. A second partial matrix is provided equivalent to the first partial matrix.