The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 05, 2017
Filed:
Feb. 23, 2016
Applicant:
Kabushiki Kaisha Toshiba, Tokyo, JP;
Inventor:
Teruo Takagiwa, Yokohama Kanagawa, JP;
Assignee:
KABUSHIKI KAISHA TOSHIBA, Tokyo, JP;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01); G11C 7/06 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 29/00 (2006.01); G11C 29/12 (2006.01); G11C 29/44 (2006.01);
U.S. Cl.
CPC ...
G11C 7/106 (2013.01); G11C 7/065 (2013.01); G11C 7/1006 (2013.01); G11C 7/1063 (2013.01); G11C 7/1087 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 29/76 (2013.01); G11C 2029/1204 (2013.01); G11C 2029/4402 (2013.01);
Abstract
A semiconductor memory device includes a plurality of memory cells, a data bus connected to a first column of the memory cells, by which data is transferred to and from the memory cells of the first column, a data latch storing data indicating whether the first column is defective or not, and a transistor having a first terminal connected to the data bus, a second terminal connected to a voltage source, and a gate connected to an output of the data latch.