The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Nov. 20, 2015
Applicant:

Headway Technologies, Inc., Milpitas, CA (US);

Inventors:

Yaguang Wei, Pleasanton, CA (US);

Yuhui Tang, Milpitas, CA (US);

Moris Dovek, San Jose, CA (US);

Yue Liu, Fremont, CA (US);

Assignee:

Headway Technologies, Inc., Milpitas, CA (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/127 (2006.01); G11B 5/31 (2006.01); G11B 5/147 (2006.01);
U.S. Cl.
CPC ...
G11B 5/315 (2013.01); G11B 5/1278 (2013.01); G11B 5/1475 (2013.01); G11B 5/3116 (2013.01);
Abstract

A PMR writer is disclosed wherein magnetic flux return from a magnetic medium to a main pole is substantially greater through a trailing shield structure than through a leading shield and return path layer (RTP). Magnetic impedance is increased between the RTP and main pole in the leading return loop by modifying the size and shape of the back gap connection (BGC), by decreasing Bs in the RTP or reducing its thickness, or by removing one or more layers in the BGC and replacing with dielectric material or non-magnetic metal to form a dielectric gap between the RTP and main pole. As a result, area density control and bit error rate are improved over a conventional dual write shield (DWS) structure comprising two flux return pathways. Moreover, adjacent track erasure is maintained at a level similar to a DWS design.


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