The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Mar. 11, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

John W. Brothers, Calistoga, CA (US);

Santosh Abraham, Pleasanton, CA (US);

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06T 11/00 (2006.01); H04N 19/00 (2014.01); H04N 19/176 (2014.01); G06F 9/45 (2006.01); G06F 9/38 (2006.01); G06T 1/60 (2006.01); G09G 5/36 (2006.01); G09G 5/393 (2006.01); G06T 11/40 (2006.01);
U.S. Cl.
CPC ...
G06T 1/60 (2013.01); G06F 8/433 (2013.01); G06F 9/3838 (2013.01); G06T 11/40 (2013.01); G09G 5/363 (2013.01); G09G 5/393 (2013.01); G09G 2350/00 (2013.01); G09G 2360/121 (2013.01);
Abstract

A graphics processing operation may include a set of render target operations, in which render targets are read and one or more intermediate computations are performed before generating final render target output. A method of performing graphics processing includes determining a dependency between render targets and defining a scheduling of tiles to reduce or eliminate a need to write intermediate computations to external memory. An interleaved order may be determined to maintain intermediate computations of dependent render target operations in an on-chip cache hierarchy.


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