The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 05, 2017

Filed:

Jan. 14, 2015
Applicant:

Arm Limited, Cambridge, GB;

Inventors:

Andreas Due Engh-Halstvedt, Trondheim, NO;

Ian Victor Devereux, Cambridge, GB;

David Bermingham, Cambridge, GB;

Jakob Axel Fries, Malmo, SE;

Oskar Lars Flordal, Lund, SE;

Assignee:

ARM Limited, Cambridge, GB;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 9/38 (2006.01); G06F 12/08 (2016.01); G06F 12/0855 (2016.01);
U.S. Cl.
CPC ...
G06F 9/3869 (2013.01); G06F 9/3816 (2013.01); G06F 12/0855 (2013.01); G06F 9/38 (2013.01); G06F 9/3855 (2013.01); G06F 9/3867 (2013.01); G06F 2212/455 (2013.01);
Abstract

A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.


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