High bandwidth memory and glitch-less differential xor

Abstract

A high-bandwidth multiple-read memory device includes multiple memory blocks, multiple address input buses, and a number of output data buses. The memory blocks include an auxiliary memory block and each memory block include several memory sub-blocks including an auxiliary memory sub-block. The output data buses output data corresponding to addresses corresponding to the address input buses during a multiple-read operation. The addresses correspond to a single memory sub-block of the memory sub-blocks of a memory block. Also described is differential XOR circuit that includes a selection logic circuit, a precharger circuit, and a multiplexer. The selection logic circuit provides a complementary output signal corresponding to a single-ended input signal. The multiplexer provides, during an evaluate phase, a differential output signal.