The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Oct. 28, 2015
Advanced Charging Technologies, Llc, Tulsa, OK (US);
Michael H. Freeman, Tulsa, OK (US);
W. J. Weaver, Jr., Broken Arrow, OK (US);
Mitchael C. Freeman, Sapupla, OK (US);
Robert Dieter, Owasso, OK (US);
Andrea Baschirotto, Tortona, IT;
Piero Malcovati, Pavia, IT;
Marco Grassi, Tulsa, OK (US);
Glenn Noufer, Manitou Springs, CO (US);
Randall L. Sandusky, Divide, CO (US);
Neaz Farooqi, Colorado Springs, CO (US);
Jim Devoy, Florissant, CO (US);
Silvia Jaeckel, Tulsa, OK (US);
Madison Hayes Yarbro Freeman, Tulsa, OK (US);
Advanced Charging Technologies, LLC, Tulsa, OK (US);
Abstract
An electrical circuit for providing electrical power for use in powering electronic devices, such as monitors, televisions, white goods, data centers, and telecom circuit boards, is described herein. The electrical circuit includes an input terminal configured to receive an input power signal, an output terminal configured to provide an output power signal, and a plurality of voltage reduction circuit cells coupled between the input terminal and the output terminal. Each of the voltage reduction circuit cells includes a pair of flyback capacitors, a switching circuit, and a hold capacitor. The switching device is configured to operate the corresponding voltage reduction circuit cell at a charging phase and at a discharging phase. The plurality of voltage reduction circuit cells are configured to deliver the output power signal having a voltage level that is less than the voltage level of the input power signal.