The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Jul. 28, 2015
Applicant:

University of South Florida, Tampa, FL (US);

Inventors:

Selcuk Kose, Tampa, FL (US);

Orhun Aras Uzun, Tampa, FL (US);

Weize Yu, Tampa, FL (US);

Assignee:

UNIVERSITY OF SOUTH FLORIDA, Tampa, FL (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H02M 3/158 (2006.01); H02M 3/07 (2006.01);
U.S. Cl.
CPC ...
H02M 3/07 (2013.01);
Abstract

Dynamic power management techniques and voltage converter architectures are described to provide a secure and efficient on-chip power delivery system. In aspects of the embodiments, converter-gating is used to adaptively turn individual interleaved switched-capacitor stages of a voltage converter on and off based on workload information to improve voltage conversion efficiency. Further, as a countermeasure against machine learning based differential power analysis attacks, for example, control signals provided to a number of the interleaved switched-capacitor stages are delayed to reduce the risk of low power trace entropy (PTE). A higher PTE value is maintained regardless of the phase difference between an attacker's sampling rate and the operating frequency, providing an additional layer of security.


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