The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Oct. 14, 2015
Applicant:

SK Hynix Inc., Gyeonggi-do, KR;

Inventors:

Gyu Hyun Kim, Gyeonggi-do, KR;

Dae Won Kim, Gyeonggi-do, KR;

Byoung Ki Lee, Gyeonggi-do, KR;

Han Woo Cho, Gyeonggi-do, KR;

Assignee:

SK Hynix Inc., Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 45/00 (2006.01);
U.S. Cl.
CPC ...
H01L 45/1675 (2013.01); H01L 45/06 (2013.01); H01L 45/1233 (2013.01); H01L 45/1253 (2013.01); H01L 45/144 (2013.01); H01L 45/16 (2013.01);
Abstract

A method of semiconductor device fabrication that includes sequentially forming an interfacial conductive layer and an etch stop layer on a resistive memory layer; forming a main conductive layer on the etch stop layer; exposing a portion of the etch stop layer by patterning the main conductive layer; exposing a portion of the interfacial conductive layer by patterning the portion of the etch stop layer; forming an upper electrode structure by patterning the portion of the interfacial conductive layer; cleaning a surface of the upper electrode structure and an exposed surface of the resistive memory layer; and patterning the resistive memory layer using the upper electrode structure as an etch mask.


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