The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 9748378 B1

PDF
Full Text
Expired
Date of Patent:
Aug. 29, 2017

Filed:

Mar. 12, 2015
Applicant:

Infineon Technologies Ag, Neubiberg, DE;

Inventors:

Karoline Koepp, Munich, DE;

Andreas Meiser, Sauerlach, DE;

Till Schloesser, Munich, DE;

Assignee:

Infineon Technologies AG, Neubiberg, DE;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/088 (2006.01); H01L 29/78 (2006.01); H01L 29/40 (2006.01); H01L 29/423 (2006.01); H01L 29/66 (2006.01); H01L 29/06 (2006.01);
U.S. Cl.
CPC ...
H01L 29/7825 (2013.01); H01L 27/088 (2013.01); H01L 29/407 (2013.01); H01L 29/4236 (2013.01); H01L 29/66681 (2013.01); H01L 29/7813 (2013.01); H01L 29/7823 (2013.01); H01L 29/7835 (2013.01); H01L 29/0692 (2013.01); H01L 29/0696 (2013.01);
Abstract

A semiconductor device includes a transistor in a semiconductor substrate having a first main surface. The transistor includes a source region, a drain region, a channel region, a drift zone, and a gate electrode adjacent to at least two sides of the channel region. The gate electrode is disposed in trenches extending in a first direction parallel to the first main surface. The gate electrode is electrically coupled to a gate terminal. The channel region and the drift zone are disposed along the first direction between the source region and the drain region. The semiconductor device further includes a conductive layer beneath the gate electrode and insulated from the gate electrode. The conductive layer is electrically connected to the gate terminal.


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