The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

May. 26, 2016
Applicant:

Omnivision Technologies, Inc., Santa Clara, CA (US);

Inventors:

Yin Qian, Milpitas, CA (US);

Dyson H. Tai, San Jose, CA (US);

Jin Li, San Jose, CA (US);

Chen-Wei Lu, San Jose, CA (US);

Howard E. Rhodes, Nokomis, FL (US);

Assignee:

OmniVision Technologies, Inc., Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/10 (2006.01); H01L 27/146 (2006.01);
U.S. Cl.
CPC ...
H01L 27/14687 (2013.01); H01L 27/1464 (2013.01); H01L 27/1469 (2013.01); H01L 27/14634 (2013.01); H01L 27/14636 (2013.01); H01L 27/14689 (2013.01);
Abstract

A method of fabricating an image system includes forming a first wafer that includes a first semiconductor substrate and a first interconnect layer. A pixel array is formed in an imaging region of the first semiconductor substrate and a first insulation-filled trench is formed in a peripheral circuit region of the first semiconductor substrate. Additionally, a second wafer is formed that includes a second semiconductor substrate and a second interconnect layer. A second insulation-filled trench is formed in a second semiconductor substrate, and the first wafer is bonded to the second wafer. A third interconnect layer of a third wafer is bonded to the second wafer. At least one deep via cavity is formed through the first and second interconnect layers and through the first and second insulation-filled trenches. The at least one deep via cavity is filled with a conductive material to form a deep via.


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