The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

May. 26, 2015
Applicant:

Samsung Display Co., Ltd., Yongin, KR;

Inventors:

Myounghwa Kim, Yongin, KR;

Jaewook Kang, Yongin, KR;

Joohee Jeon, Yongin, KR;

Jongchan Lee, Yongin, KR;

Yoonho Khang, Yongin, KR;

Assignee:

Samsung Display Co., Ltd., Yongin-si, KR;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/12 (2006.01); H01L 29/786 (2006.01); H01L 29/423 (2006.01); H01L 29/49 (2006.01); H01L 29/45 (2006.01); G02F 1/1368 (2006.01); H01L 27/32 (2006.01); G02F 1/1362 (2006.01);
U.S. Cl.
CPC ...
H01L 27/1255 (2013.01); G02F 1/1368 (2013.01); H01L 27/1222 (2013.01); H01L 27/1288 (2013.01); H01L 29/42372 (2013.01); H01L 29/42384 (2013.01); H01L 29/458 (2013.01); H01L 29/4908 (2013.01); H01L 29/4966 (2013.01); H01L 29/78666 (2013.01); H01L 29/78675 (2013.01); G02F 1/136213 (2013.01); H01L 27/3258 (2013.01); H01L 27/3262 (2013.01); H01L 27/3265 (2013.01); H01L 2227/323 (2013.01);
Abstract

Provided is a thin film transistor array substrate having at least one thin film transistor. The thin film transistor includes a semiconductor layer having a channel area with a first doping concentration on a substrate, a source-drain area disposed at opposite sides of the channel area and with a second doping concentration greater than the first doping concentration, and a substantially undoped area extending from the source-drain area. The substrate has a gate insulating layer on the semiconductor layer and a gate electrode disposed on the gate insulating layer and overlapping the channel area in at least some portions. The substrate has a source electrode and a drain electrode, each insulated from the gate electrode and electrically connected to the source-drain area. The gate electrode includes a first gate electrode layer and a second gate electrode layer, wherein the second gate electrode layer is thicker than the first gate electrode layer.


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