The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

May. 20, 2016
Applicant:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Inventors:

Takahiko Ishizu, Kanagawa, JP;

Shuhei Nagatsuka, Kanagawa, JP;

Tatsuya Onuki, Kanagawa, JP;

Yutaka Shionoiri, Kanagawa, JP;

Naoaki Tsutsui, Kanagawa, JP;

Shunpei Yamazaki, Tokyo, JP;

Assignee:

Semiconductor Energy Laboratory Co., Ltd., Atsugi-shi, Kanagawa-ken, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/401 (2006.01); H01L 27/12 (2006.01); G11C 5/06 (2006.01); G11C 11/4097 (2006.01); G11C 29/04 (2006.01); H01L 27/108 (2006.01); H01L 27/1156 (2017.01);
U.S. Cl.
CPC ...
H01L 27/1207 (2013.01); G11C 5/063 (2013.01); G11C 11/401 (2013.01); H01L 27/1225 (2013.01); H01L 27/1255 (2013.01); G11C 11/4097 (2013.01); G11C 2029/0403 (2013.01); H01L 27/108 (2013.01); H01L 27/1156 (2013.01);
Abstract

A memory device in which the number of films is reduced. The memory device includes a circuit and a wiring. The circuit includes a first memory cell and a second memory cell. The first memory cell includes a first transistor, a second transistor, and a first capacitor. The second memory cell includes a third transistor, a fourth transistor, and a second capacitor. The second memory cell is stacked over the first memory cell. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and the first capacitor. One of a source and a drain of the third transistor is electrically connected to a gate of the fourth transistor and the second capacitor. A gate of the first transistor and a gate of the third transistor are electrically connected to the wiring.


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