The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 29, 2017
Filed:
Aug. 11, 2014
Applicant:
Fitipower Integrated Technology, Inc., Hsinchu, TW;
Inventor:
Chih-Nan Cheng, Hsinchu, TW;
Assignee:
Fitipower Integrated Technology, Inc., Hsinchu, TW;
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01); H01L 29/06 (2006.01); H01L 21/265 (2006.01); H01L 29/423 (2006.01); H01L 29/08 (2006.01);
U.S. Cl.
CPC ...
H01L 27/0266 (2013.01); H01L 29/0626 (2013.01); H01L 29/66681 (2013.01); H01L 29/7818 (2013.01); H01L 21/26513 (2013.01); H01L 29/0653 (2013.01); H01L 29/0878 (2013.01); H01L 29/42368 (2013.01);
Abstract
An electrostatic discharge (ESD) protection device includes two N-metal oxide semiconductor (NMOS) elements and a doped region. The two NMOS elements are arranged on a P-substrate, and each NMOS element includes a gate, a source, and a drain. The source and the drain are arranged on two opposite sides of the gate. The doped region is implanted into an outer space of the two NMOS surrounding the two NMOS, and a PN junction is formed by the doped region and the P-substrate.