The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Apr. 28, 2015
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, KR;

Inventors:

Young-ja Kim, Asan-si, KR;

Jun-young Ko, Cheonan-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H05K 3/34 (2006.01); H05K 1/11 (2006.01); H01L 23/00 (2006.01); H01L 23/498 (2006.01);
U.S. Cl.
CPC ...
H01L 24/17 (2013.01); H01L 23/49838 (2013.01); H01L 24/16 (2013.01); H05K 3/3452 (2013.01); H01L 23/49816 (2013.01); H01L 2224/131 (2013.01); H01L 2224/13082 (2013.01); H01L 2224/13144 (2013.01); H01L 2224/13147 (2013.01); H01L 2224/13155 (2013.01); H01L 2224/16013 (2013.01); H01L 2224/16058 (2013.01); H01L 2224/16105 (2013.01); H01L 2224/16113 (2013.01); H01L 2224/16237 (2013.01); H01L 2224/16238 (2013.01); H01L 2224/17051 (2013.01); H01L 2224/17104 (2013.01); H01L 2224/73204 (2013.01); H01L 2224/81191 (2013.01); H01L 2224/81194 (2013.01); H01L 2924/13091 (2013.01); H01L 2924/15311 (2013.01); H05K 1/111 (2013.01); H05K 3/3436 (2013.01); H05K 2201/0989 (2013.01); H05K 2201/09227 (2013.01); H05K 2201/09909 (2013.01);
Abstract

A printed circuit board (PCB) includes: a base substrate including a top surface including an electronic device mounting region; chip connection pads that are provided on the electronic device mounting region; a conductive pattern group that is provided on the top surface of the base substrate and includes an extended conductive pattern extending between two adjacent chip connection pads from among the chip connection pads, the extended conductive pattern being spaced apart from each of the two adjacent chip connection pads; and a solder resist layer that covers a part of the extended conductive pattern and is spaced apart from the chip connection pads.


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