The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Aug. 29, 2017

Filed:

Jul. 11, 2016
Applicant:

Samsung Electronics Co., Ltd., Suwon-si, Gyeonggi-do, KR;

Inventors:

Inkyeong Yoo, Yongin-si, KR;

Hojung Kim, Suwon-si, KR;

Seongho Cho, Gwacheon-si, KR;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 16/04 (2006.01); H01L 27/11568 (2017.01); H01L 23/528 (2006.01); H01L 45/00 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/14 (2006.01);
U.S. Cl.
CPC ...
G11C 16/0466 (2013.01); G11C 16/10 (2013.01); G11C 16/14 (2013.01); G11C 16/26 (2013.01); H01L 23/528 (2013.01); H01L 27/11568 (2013.01); H01L 45/08 (2013.01); H01L 45/1233 (2013.01); H01L 45/146 (2013.01);
Abstract

A non-volatile inverter may be configured to perform a memory function. The non-volatile inverter may include first and second transistors. The first transistor may include a first gate electrode, a first electrode, and a second electrode. The second transistor may include a second gate electrode and a third electrode and may share the second electrode with the first transistor. The first transistor may include a first switching layer and a charge trap layer. The first switching layer may be configured to switch between a high resistance state and a low resistance state. The charge trap layer may be configured to trap or de-trap charges according to the resistance state of the first switching layer. The first switching layer may include a P-N diode. The second transistor may include a second gate switching layer and a charge trap layer.


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